The invention relates to an integrated circuit structure comprising capacitive means of decoupling power supply terminals from the circuit.
It is used for applications in the fields of micro-electronics for making circuits with MOS, MIS or bipolar components, and to reduce parasite noise generated on electrical power supplies for circuits caused particularly by transient current demand.
More precisely, the invention may be used in, portable appliances for example such as microprocessors, cordless telephony circuits or any other applications using SOI technologies for their low consumption characteristics.
In integrated circuits, the distribution of grounds and power supply potentials to active devices, in other words for example to transistors, is achieved by using power supply tracks made of an electrically conducting material. During operation of the circuits, the power supply tracks must output transient currents with a relatively high intensity.
These transient currents can generate parasite noise on tracks and the power supply system, depending on their intensity and location.
Filtering capacitors are usually used in electronic circuits connected between the terminals of power supply systems to reduce parasite noise, and are placed as close as possible to the transient current source.
In the field of integrated electronics, the manufacture of filtering capacitors can cause problems. However, the structure of some types of integrated circuits such as CMOS (Complementary Metal Oxide Semiconductor) circuits on solid substrates can naturally decouple power supply potentials and the ground potential.
FIG. 1 is a diagrammatic view through part of a typical CMOS type of integrated circuit.
In this figure, reference 10 denotes a solid silicon substrate with a P type of conductivity. An N type caisson 12 is formed in this substrate. References 14 and 16 denote field effect transistors made in the P type substrate and in the N type caisson respectively.
Strongly doped active areas 14a, 14b, 16a, 16b, 18 and 20 form sources and drains of field effect transistors 14, 16, and contact areas for the P and N type regions, respectively.
The P+ type active area 18 is in contact with the P type substrate and the N+ type active area 20 is in contact with the N type caisson.
A thick electrical insulating layer 22 covers the substrate and components 14, 16 that are made on it. Openings 24 pass through this layer, and an electrically conducting material is stacked on it in order to connect the active areas to conducting tracks 26, 28, 30 formed above the electrical insulating layer 22. The openings filled with an electrical conducting material are also called xe2x80x9cviasxe2x80x9d.
The vias connect active areas to each other. For example, this is the case of vias connected to the central conducting track 26 that electrically connect the active areas 14b and 16a to each other. The vias also connect active areas and/or regions of the substrate to power supply terminals.
In FIG. 1, the power supply terminals consist of conducting tracks 28 and 30 that are connected to a power supply source 31 diagrammatically shown as continuous lines.
The conducting track 28 forms a ground terminal. It is connected to the active area 14a of the first transistor 14, and to the substrate 10 through the active area 18. A second power supply terminal formed by the conducting track 30 is connected particularly to caisson 12 through the active area 20.
The caisson 12 forms a semi-conducting junction with the substrate 10 which has a certain junction capacity and which is connected between the power supply terminals 28, 30 in parallel with the components.
Thus the capacitance of the caisson-substrate junction filters the power supply and reduces parasite noise due to current demand.
There are other types of CMOS structures with N caissons, P caissons or double caissons. Junction capacitors formed between the caissons and the substrate are usually sufficient to obtain intrinsic decoupling between the ground terminal and the other power supply terminals.
However, a number of integrated circuits made at the present time are not formed on a solid substrate as mentioned above, but are formed in a thin layer of a support with a Silicon On Insulator type structure. This type of structure, usually denoted xe2x80x9cSOIxe2x80x9d, comprises an electrically insulating material, for example oxide, that separates the thin layer of silicon from a solid part of the support. Making integrated circuits on SOI type substrates can increase the integration density, reduce parasite capacitances and improve performances of circuits in terms of operating frequency and consumption.
In the case of circuits made on SOI substrates, the insulation between the different components or active areas is formed by oxide areas.
Thus, decoupling between grounds and other power supply terminals through the substrate in structures on a solid substrate is much weaker in circuits made on SOI type substrates.
Therefore, higher noise is observed in these circuits. For example, this problem is described in document (1), for which the reference is given at the end of this description.
One possible solution for reducing parasite noise consists of adding decoupling capacitors to the integrated circuit formed in the thin layer of the SOI structure. These capacitors may be made using the grid capacitor of one or several transistors. For example, an NMOS type transistor can be used in which the grid is connected to a power supply terminal and in which the source and drain are connected to the ground. A better quality capacitance can be achieved by using an appropriate layout of the channel in such a transistor.
However, transistors or other capacitors dedicated to decoupling power supply terminals are placed on the SOI structure adjacent to transistors forming the functional part of the integrated circuit. Thus, they occupy useful space thus increasing the total area of electronic chips.
Further information on this subject can be found in documents (2) and (3), for which the references are given at the end of the description.
Technological background of the invention is also illustrated in document (4).
The purpose of this invention is to propose an integrated circuit formed in a thin insulated layer of a substrate, for example such as a thin layer of an SOI substrate which does not have the limitations mentioned above.
One particular purpose is to propose a circuit including means of decoupling the terminals of one or several power supplies in order to efficiently reduce the parasite noise in power supplies.
Another purpose is to propose such a circuit using a chip with a small surface area.
In order to achieve these objectives, the purpose of the invention is an integrated circuit comprising:
at least one first and one second power supply terminal,
at least one active area formed in a thin layer of a substrate and electrically connected to at least one of the power supply terminals.
According to the invention, the integrated circuit also comprises capacitive decoupling means formed by at least one dielectric capacitor connected between the said first and second power supply terminals and formed in a region of the substrate that is electrically insulated from the thin substrate layer.
For the purposes of this invention, an active area is an area of the thin layer with a determined type of doping. An electronic circuit can include a very large number of active areas that in particular can form parts of transistors such as transistor sources or drains.
Furthermore, power may be supplied to the circuit by one or several power supplies. A power supply terminal is a conducting element connected to a power supply, the potential of which is fixed by the said power supply. The ground terminal is one particular power supply terminal.
With the invention, the capacitive decoupling means do not reduce the available space for functional components of the integrated circuit, in other words for the active areas, since they are not formed in the thin layer.
According to one particular advantageous aspect, the region comprising capacitive decoupling means may extend at least partly below the active area(s) of the integrated circuit.
This characteristic makes an even greater contribution to reducing the total area of the chip used in the circuit.
The capacitive decoupling means in the invention may comprise one or several dielectric capacitors. A dielectric capacitor is a capacitor made in the same way as a conventional capacitor, in other words with two foils made of an electrically conducting material separated by an electrically insulating material.
Thus, the substrate region insulated from the thin layer may comprise at least a first and at least a second layer of an electrically conducting material electrically insulated from each other, with at least one surface facing the other and connected to the first and second power supply terminals respectively.
The first and second layers of conducting material, for example made of doped silicon or polycrystalline silicon, may be separated by a silicon oxide layer.
According to one improvement of the invention, the capacitive decoupling means may comprise at least one electrically conducting layer forming a foil of the capacitor, and connected to at least one active area to connect the said active area to a power supply terminal.
The use of decoupling means to distribute an electrical power supply to active areas is not only very useful to even further reduce parasite noise, but also to release a large area to make interconnection tracks for active parts and for signal transport. These tracks are usually-formed on one side of the thin layer opposite the solid part of the SOI substrate.
The invention also relates to a process for making an integrated circuit equipped with capacitive dielectric means. This process comprises the following steps in sequence:
a) formation of a first insulating layer and a second conducting layer in order, starting from the surface, on a substrate comprising a first conducting layer,
b) formation of the second conducting layer to leave at least part of the second conducting layer separated from the first conducting layer by the first insulating layer,
c) formation of a second insulating layer surrounding part of the second conducting layer,
d) creation of a thin layer of semiconducting material on the second insulating layer,
e) formation of at least one component in the thin layer, comprising at least one active area and oxidation of the thin layer between the components,
f) formation of a thick electrical insulating layer on the thin layer,
g) formation of openings passing through the thick insulating layer, the thin layer, and the layer of electrical insulating material outside components to reach the first and second conducting layers,
h) placement of the conducting material in the openings, and formation of electrical interconnections to connect the first and second conducting layers to first and second electrical power supply terminals, respectively.
Step g) can also comprise the formation . of openings passing through the thick insulating layer to reach active areas in the thin layer, these openings also being filled with electrical conducting material to selectively connect active areas to each other or to connect active areas to electrical power supply terminals.
Other characteristics and advantages of this invention will become clearer from the following description with reference to the figures in the attached drawings. This description is given for illustrative purposes only and is in no way restrictive.